리얼지니어스

https://www.eetimes.com/guc-taped-out-ucie-32g-ip-using-tsmcs-3nm-and-cowos-technology/ GUC Taped Out UCIe 32G IP using TSMC’s 3nm and CoWoS Technology - EE Times Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced that it has successfully taped out Universal Chiplet Interconnect Express™ www.eetimes.com GUC는 자체 개발하던 GLink2.5D family는 향후 어떻게 되는 지 궁금하다. 모두가 UCIe 로 모이는 것인 지. 속도 32Gbps가..

https://www.electronicdesign.com/technologies/eda/video/21279211/accenture-can-chiplets-solve-semiconductor-challenges Can Chiplets Solve Semiconductor Challenges? With the right investments, chiplets can help solve long-standing industry challenges such as increasing costs and supply disruptions, resulting in a world where devices are more... www.electronicdesign.com Manufactoring a chip on a s..

https://semiengineering.com/knowledge_centers/low-power/techniques/power-isolation/ Power Isolation Logic used to isolate signals between two power domains where one is switched on and one is switched off. The most common usage of such cell is to isolate signals originating in a power domain that is being switched off, from the power domain that receives semiengineering.com Logic used to isolate..

AMD Shares New Second-Gen 3D V-Cache Chiplet Details, up to 2.5TB/s, tom's Hardware, Link 저 V-cache가 업그레이드가 된 것. Row 0 - Cell 0 2nd-Gen 7nm 3D V-Cache Die First-Gen 7nm 3D V-Cache Die 5nm Zen 4 Core Complex Die (CCD) 7nm Zen 3 Core Complex Die (CCD) Size 36mm^2 41mm^2 66.3 mm^2 80.7mm^2 Transistor Count ~4.7 Billion 4.7 Billion 6.57 Billion 4.15 Billion MTr/mm^2 (Transistor Density) ~130.6 Milli..

이 기사는 영어자체가 굉장히 화려해서, 문장 자체를 옮겨 놓고자 한다. 나도 이런 영어를 구사해보고 싶다. As is usually the case, I'm astonished and astounded by the leaps in technology that are occurring all around me. Things are now moving so fast that there will probably be yet another mindboggling development before I've finished this column. The generation of electronics engineers that came before your hhumble narrator (as you know, I ..

자료를 구할 수 없어서 아쉬워 하는 중. ISC2023 발표자료인데, 어디서 구할 수 있을 수도 있지 않을까. https://www.hpcwire.com/2023/06/07/for-the-first-time-ucie-shares-bandwidth-speeds-between-chiplets/ For the First Time, UCIe Shares Bandwidth Speeds Between Chiplets The first numbers of the available bandwidth between chiplets is out – UCIe is estimating that chiplet packages could squeeze out communication speeds of 630Gbps, or 0.6..

VCD: Value/Variable Change Dump ASCII file deifned in the IEEE1364 standard(Verilog HDL language standrad) Event based format which contains every value change for the signals in the design and the time at which they occured VCD는 PTPX의 average mode와 time-based analysis mode를 둘다 지원한다. Gate-level VCD 와 RTL-lvel VCD 가 이용되지만, RTL-level VCD를 사용할 때는 set_rtl_to_gate_name 을 통해서 name mapping을 설정해줘야 한다. E..

TSMC CoWoS, InFO TSMC는 wafer level에서 여러가지 패키징 기술을 제공한다. InFo와 CoWos는 TSMC에서 만든 패키징 브랜드 이름이다. 이 두 가지 기술은 FanOut Wafer Level category에 속한다. 연결방식에 따라서 CoWoS-S,R,L로 나뉜다. Apple은 iphone7에서 InFo를 적극 채용했었다. Info는 모바일 용, CoWoS는 HPC용이다. To be continue...