[Article] Can Chiplets Solve Semiconductor Challenges?

https://www.electronicdesign.com/technologies/eda/video/21279211/accenture-can-chiplets-solve-semiconductor-challenges

Can Chiplets Solve Semiconductor Challenges?

 

Manufactoring a chip on a single piece of silicon has led to skyrocketing costs.

One path to achieve the same level of performance at a fraction of the cost is by combining chipsets with different functions. There are three mainstream architecture designs for compiling chiplets:

 

1. Fan-out: It utilizes dice and redistribution layers to combine different chiplets. Fan-out isn't as fast or power efficient as other architecture systems, but it's more easily testable and therefore has a faster time-to-market.
2. 2.5D: It uses an interposer for stacked inter-chiplet communication, leading to a higher communication rate. It can be paired with stacked memory modules to create high-performance modules. However, the interposers that enable 2.5D architecture are expensive relative to the other methods.
3. 3D: It is the same general idea as 2.5D with chip stacking, but it involves stacking logic on logic chiplets with through silicon vias (TSVs) to yield thehighest-performance chip designs.

AMD, Intel have designed their own chiplets and interconnects for some time, although mostly through proprietary componenets and design. Now, other semiconductor firms like NVIDIA~~ diminishing power, performance benefits, growing complexity and cost of scaling.

 

This shift hasn't gone unnoticed by countries looking to bolster dometic manufacturing either. The U.S. chips and Science Act authorized $2.5B last yer for an advanced-pakaging R&D program, while China is offereing tas breaks and incentives for similar investments.

 

Challenges Remain for Chiplets

The concept of chiplet isn't new.

It will be much more difficult to create a commercial chiplet marketplace in which chiplets from multiple vendors are developed according to the agreed standards...so that they're compatible with one another and truly plug-and-play.

 

To realize the potential of chiplets as the next frontier in semiconductor innovation, sourcing, manufacturing, and packaging must happen in a standardized, repeatable, and scalable fashion.

 

Carving a Path Toward a Smart World.

At a time when manufacturing advanced nodes and achieving Moore's Lae is becoming increasingly complex and cost prohibitive, chiplets appear as a viable way forward to obtain design flexibility, reduce development time and costs, and lower power consumption. But doing so will require a coordinated effort that involves reimagining semiconductor ecosystem needs to allow for industry-wide interoperability and integration.